1. Field of the Invention
The present invention relates to a parallel scrambling system for parallel scrambling signals generated in systems using M-bit (M&gt;1) interleaved multiplexer/demultiplexer.
2. Description of the Prior Art
Referring to FIG. 1A, there is illustrated a conventional system using an M-bit (M&gt;1) interleaved multiplexer. As shown in FIG. 1A, the system comprises an M-bit interleaved multiplexer 11 for multiplexing input signals A.sub.0 to A.sub.N-1 and a serial scrambler 12 for serial scrambling a multiplexed transmission signal from the multiplexer 11 to generate a scrambled signal B. On the other hand, another conventional system using an M-bit interleaved demultiplexer (M&gt;1) is illustrated in FIG. 1B. As shown in FIG. 1B, this system comprises a serial descrambler 15 for receiving and descrambling the scrambled signal B and an M-bit interleaved demultiplexer 16 for demultiplexing a descrambled signal from the descrambler 15 to make the original signals A.sub.0 to A.sub.N-1 recover. The serial scrambler 12 includes a serial shift register sequence generator 13 and an exclusive OR gate circuit 17. In similar, the serial descrambler 15 includes a serial shift register sequence generator 14 and an exclusive OR gate circuit 18 both of which have the same constructions as those of the serial scrambler 12, respectively.
In FIGS. 1A and 1B, the reference letter S denotes shift register sequences generated in the serial shift register sequence generators 13 and 14, and B scrambled signals. In the systems shown in FIG. 1A and 1B, serial shift register sequence generators 13 and 14 may be either of a simple shift register generator or a modular shift register generator. FIG. 2A shows a configuration of the simple shift register generator, while FIG. 2B shows a configuration of the modular shift register generator. Also, FIG. 2C shows a practical circuit employing D-type flip-flops and a XOR gate to embody the configuration of FIG. 2A.
Each block shown in FIGS. 2A and 2B denotes a shift register (or a flip-flop). The number 1 or 0 written in each block indicates an initial state value of the corresponding shift register.
A representative example of systems using the above-mentioned M-bit interleaved multiplexer is a synchronous digital hierarchy (SDH) based system proposed by CCITT. This system adopts M=8.
However, such a conventional scrambling system comprises high-rate processing elements for enabling a scrambling of high-rate transmission signals produced by multiplexing signals inputted in a multiplexer, where each input signal corresponds to a synchronous transport module-1 (STM-1) signals with its transmission rate being 155.520 Mbps. Due to such high-rate processing elements, there are disadvantages in terms of manufacture cost and electric power consumption.
Where the input signals are 16 STM-1 signals, this scrambling system should be embodied by using higher-rate processing elements of 2.48 GHz to scramble the transmission signals STM-16 produced after multiplexing. However, such elements can be hardly embodied.